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data sheet no. pd60224 rev.a IRMCK201 high performance configurable digital ac servo control ic features ? complete closed loop current control (synchronously rotating frame field orientation) ? versatile space vector pwm ? direct interface to ir2175 current sensing high voltage ic ? direct encoder interface with multiplexed/non- multiplexed hall a/b/c signals ? direct interface to ir213x 3-phase gate driver ic ? closed loop velocity control ? configurable architecture o supports ac pm motor or induction motor o closed loop or open loop control ? asynchronous serial communication interface (rs232c, rs422) ? fast spi interface ? 4 channel 12-bit a/d interface with simultaneous sample/hold ? 8-bit parallel bus interface for microcontroller expansion (supports most 8-bit microprocessors) ? integrated brake igbt control ? servodesigner tm (configuration tool) available product summary max. clock input (sysclk) 33.3 mhz max. pll clock for current feedback 133.3 mhz closed loop current control computation time 6 sec max closed loop current loop bandwidth (-3 db) 5.5 khz closed loop velocity loop update rate 5 / 10 khz pwm carrier frequency 83.3 khz max pwm counter resolution 12 bit current feedback temp drift/offset calibrated max spi clock 8 mhz package: qfp100 description IRMCK201 is a complete ac servo motor control ic. it contai ns closed loop current control for sinusoidal ac current, and closed loop velocity control based on encoder position feedback interface. a standard communication port is provided for rs232c or rs422, in addition to a fast spi communication in terface. unlike a traditional d sp or a microcontroller, the IRMCK201 does not require any programming effort to complete th e complex control algorithm. it allows users to configure the algorithm for specific application needs. permanent magnet motor or ac induction motor are supported. IRMCK201 facilitates high performance servo design together with the ir 2175 current sensing ic and ir213x high volta ge 3-phase gate driver ic, which simplifies the hardware design while minimizing cost. for multi-ax is applications, IRMCK201 can be used as a multi-drop slave drive based on the spi protoc ol. the package is available in a 100-pin qfp.
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 2 overview IRMCK201 is a new international rectifier integrated ci rcuit device designed as a one-chip solution for complete closed loop current control and velo city control for a high performance se rvo drive system. unlike a traditional microcontroller or dsp, IRMCK201 does not require any programming to complete complex ac servo algorithm development. combined with international rectifier's high voltage gate drive and current sensing ic, the user can implement a complete ac servo control with minimum component count and virtually no design effort. although IRMCK201 contains dedicated logic to perform closed loop c ontrol of ac current and velocity, it has a wide range of application coverage through its flexib le configuration ability. the drive can be easily configured for induction machine closed loop vector control or permanent magnet motor servo drive. rich motion peripherals, analog and digital i/o can also be configured. host communication logic contains an asynchronous rs232c or rs422 communication interface, a fast slave spi interface and an 8- bit-wide host parallel inte rface. all communication ports have the same access capability to the host re gister set. the user can write to and read from the predef ined registers to configure and monitor the drive through these communication ports. IRMCK201 main features IRMCK201 contains the following functions fo r ac servo motor control applications: ? complete closed loop current control based on synchronously rotating frame field orientation ? configurable update rate with pwm carrier frequency ? configurable parameters (all pi controller gains, pi output limit range, current feedback scaling, encoder feedback scaling) ? configurable control structure for induction machine or ac permanent magnet machine (disable/enable slip gain) ? closed loop velocity control with configurable update rate ? enable/disable velocity loop ? selectable reference input for torque and speed input ? analog reference input ? rs232c/rs422 reference input ? dynamic braking control for excess dc bus voltage ? cycle-by-cycle on/off control for brake igbt ? dc bus voltage feedback ? standard encoder interface with hall abc support ? a/b quadrature signal input up to 1 mhz ? choice of separate or multip lexed hall a/b/c signal input ? auto-initialization with hall a/b/c plus z pulse input ? adaptable for any line count encoder from 200 ppr to 10,000 ppr ? 1/t counter (2 mhz) for low speed performance improvement ? space vector pwm with deadtime insertion ? ir2175 current sensing ic interface ? ir213x high voltage gate driver ic interface ? low cost serial 12 bit a/d interface w ith multiplexer and sample/hold circuit ? 4 channel analog output by pwm 0-3.3 v, 120 khz output. ? eeprom for startup initialization of internal data/parameters through host register interface at24c01a, 128 x 8 ? versatile host communication interface
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 3 rs232c or rs422 host interface fast spi slave host interf ace with multi-drop capability parallel host interface (total 12 pins) ? multiplexed data/address bus address enable rd/wr ? discrete i/o start (input) stop (input) ifbcal (input) fault clear (input) fault (output) sync (output) pwm active (output) ? led two-bit bi-color
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 4 table of contents overview ....................................................................................................................... ................................................... 2 IRMCK201 main features ......................................................................................................... ................................... 2 IRMCK201 block diagrams ........................................................................................................ .................................. 7 basic block diagram ............................................................................................................ ........................................ 7 detailed bloc k diagram......................................................................................................... ....................................... 8 input/output of IRMCK201 ....................................................................................................... ................................... 9 typical applicat ion connections................................................................................................ ................................. 13 ic crystal cloc k circuitry ..................................................................................................... ..................................... 14 low pass filter................................................................................................................ ............................................ 15 implementing the low pass filter shield ........................................................................................ ....................... 16 cp rp and cs component values.................................................................................................. ......................... 16 pll reset...................................................................................................................... .............................................. 16 dc electrical characteristics and operating conditions ......................................................................... ................ 17 absolute maxi mum ratings....................................................................................................... ................................. 17 recommended operating conditions ............................................................................................... .......................... 17 dc charact eristics ............................................................................................................. ......................................... 18 common quiescent and leakage current ........................................................................................... ....................... 18 input characteristics ? n on schmitt trigger inputs ............................................................................. ...................... 18 input characteristics ? schmitt trigger inputs ................................................................................. .......................... 18 output char acteris tics......................................................................................................... ........................................ 18 pin and i/o charact eristic table ............................................................................................... .................................. 19 power consumption .............................................................................................................. ...................................... 21 ac electrical characteristics and operating conditions ......................................................................... ................ 22 system level ac character istics................................................................................................ ................................ 22 sync pulse to sy nc pulse timing................................................................................................ ............................ 22 fault and redled response to gatekill .......................................................................................... ......... 23 host interface ac character istics.............................................................................................. ................................. 24 spi timing ..................................................................................................................... ......................................... 24 host paralle l timing ........................................................................................................... ........................................ 25 host parallel read cy cle....................................................................................................... .................................. 25 host parallel write cy cle...................................................................................................... .................................. 26
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 5 discrete i/o electri cal charact eristics ........................................................................................ ................................ 27 motion peripheral electri cal charact eristics................................................................................... ............................ 28 pwm electrical ch aracteristics ................................................................................................. ............................. 28 ir2175 interface ............................................................................................................... ...................................... 28 encoder electrical character istics............................................................................................. .............................. 29 analog to digital interface electrical char acteris tics ......................................................................... ...................... 30 adc timing..................................................................................................................... ....................................... 30 pll interface electrical character istics....................................................................................... ............................... 32 appendix a host register map.................................................................................................. .............................. 33 host paralle l access........................................................................................................... ..................................... 33 spi register access ............................................................................................................ .................................... 33 rs-232 regist er access......................................................................................................... ................................. 33 write register definitions ..................................................................................................... ..................................... 38 quadraturedecode register group (write registers).............................................................................. ............... 38 pwmconfig register gr oup (write registers) ..................................................................................... .................. 39 currentfeedbackconfig regist er group (write registers) ......................................................................... ........... 40 systemcontrol register group (write registers)................................................................................. .................. 41 currentloopconfig register group (write registers) ............................................................................. .............. 42 velocitycontrol register group (write registers)............................................................................... .................. 43 faultcontrol register gr oup (write registers) .................................................................................. .................... 45 svpwmscaler register gr oup (write registers) ................................................................................... ............... 45 diagnosticpwmcontrol register group (write registers) .......................................................................... ........... 46 systemconfig register group (write registers).................................................................................. .................. 47 directhostvoltagecontrol regist er group (write registers) ...................................................................... .......... 47 32bitquaddecode register group (write registers)............................................................................... ............... 48 eepromcontrol register s (write re gisters)...................................................................................... ...................... 49 hallsensorencoderinit (write registers ? eeprom only) .......................................................................... ......... 50 read register definitions ...................................................................................................... ..................................... 51 quadraturedecodestatus regi ster group (read registers)......................................................................... ........... 51 systemstatus register group (read registers) ................................................................................... ................... 51 dcbusvoltage register group (read registers) ................................................................................... ................. 52 focdiagnosticdata register group (read registers).............................................................................. ............... 52 faultstatus register group (read registers).................................................................................... ...................... 54 velocitystatus register group (read registers) ................................................................................. ................... 54 currentfeedbackoffset regist er group (read registers) .......................................................................... ............ 55 32bitquaddecodestatus regist er group (read registers).......................................................................... ........... 55 eepromstatus register s (read re gisters)........................................................................................ ....................... 56 focdiagnosticdatasupplement regi ster group (read registers) .................................................................... .... 57 appendix b package ............................................................................................................ ...................................... 58 appendix c errata ............................................................................................................. ....................................... 60
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 6 list of figures figure 1. basic block diagram of IRMCK201..................................................................................... ......................... 7 figure 2. detailed bloc k diagram of IRMCK201 .................................................................................. ....................... 8 figure 3. input/output of IRMCK201 ............................................................................................ ............................... 9 figure 4. typical c onnection of IRMCK201 ...................................................................................... ........................ 13 figure 5. osc illator circuit .................................................................................................. ........................................ 14 figure 6. pll low pa ss filter sh ielding....................................................................................... .............................. 15 figure 7. system leve l sync-to-sync timing.................................................................................... .................... 22 figure 8. fault and redled response to gatekill............................................................................... .......... 23 figure 9. spi timing.......................................................................................................... .......................................... 24 figure 10. host paralle l read cycl e timing .................................................................................... ........................... 25 figure 11. host paralle l write cycl e timing ................................................................................... ........................... 26 figure 12. discre te i/o timing................................................................................................ .................................... 27 figure 13. pwm timing ......................................................................................................... ..................................... 28 figure 14. ir2175 interface ................................................................................................... ...................................... 28 figure 15. encoder timing ..................................................................................................... ..................................... 29 figure 16. top level adc timing............................................................................................... ............................... 30 figure 17. adc specific timing ................................................................................................ ................................. 31 list of tables table 1: typical values for the clock circuit .................................................................................. .............................. 14 table 2: pll test pin assignments.............................................................................................. .................................. 15 table 3: pll low pass filter values ............................................................................................ ................................. 16 table 4: absolute maximum ratings .............................................................................................. ............................... 17 table 5: recommended operating conditions ...................................................................................... ......................... 17 table 6: dc ch aracteristics .................................................................................................... ........................................ 18 table 7: non schmitt trigge r input char acteris tics ............................................................................. .......................... 18 table 8: schmitt trigger input charact eristics ................................................................................. .............................. 18 table 9: output character istics................................................................................................ ....................................... 18 table 10: pin and i/ o character istics .......................................................................................... ................................... 21 table 11: IRMCK201 po wer consumption........................................................................................... ......................... 21 table 12: system level sync-to-sync timing ..................................................................................... ..................... 23 table 13: fault and redled response to gatekill ................................................................................ ........... 23 table 14: spi timing ........................................................................................................... ........................................... 24 table 15: host paralle l read cycl e timing...................................................................................... .............................. 25 table 16: host paralle l write cycl e timing..................................................................................... .............................. 26 table 17: discre te i/o timing .................................................................................................. ...................................... 27 table 18: pw m timing ........................................................................................................... ....................................... 28 table 19: ir2175 interface ..................................................................................................... ........................................ 28 table 20: encoder timing ....................................................................................................... ....................................... 29 table 21: top le vel adc timing................................................................................................. ................................. 30 table 22: adc sp ecific timing .................................................................................................. ................................... 31 table 23: pll electri cal charact eristics....................................................................................... .................................. 32 table 24: qfp100 package....................................................................................................... ...................................... 58 table 25: qfp100 dimensions .................................................................................................... ................................... 59
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 7 IRMCK201 block diagrams basic block diagram figure 1 shows the basic block diagram of the irmc k201 surrounded by various a ccelerator ics. host communications are provided over spi, rs-232c or host parallel ports. two current sensing ics (ir2175) and a three phase high voltage gate drive typically implement th e high voltage / current interface between the IRMCK201 ic and motor. the IRMCK201 can operate in a ?stand-alone? mode without the host controller. a serial eeprom could be utilized to load motor-specific parameters into the ic. multi-axis host or other host controller ir2175 ir2175 IRMCK201 motor ac power imotion chip set tm encoder rs232c or rs422 j e j e quadrature decoding 1/t counter speed measurement 2/3 ks dt ++ dead time host register interface configuration registers monitoring registers spi interface space vector pwm period/duty counters period/duty counters brake fault + - - + - + a/d interface a/d mux select dc bus dynamic brake control analog speed reference dc bus feedback parallel interface ir2136 iramx16up60a igbt module eeprom figure 1. basic block diagram of IRMCK201
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 8 detailed block diagram figure 2 shows a detailed block diagram or the IRMCK201. all logic and algorithms are pre-programmed, and the user does not need to make any effort to develop code, alle viating the tedious design process. if needed, the user can configure the drive to tailor the control per specific needs to meet the required specification. this configuration is easily done by accessing the host register set through the communication interface. pi pi j e j e quadrature decoding 2/3 dt + + dea d time space vector pwm ir2175 interface ir2175 interface clk brake fault + - - + ads7818 a/d interface dc bus dynamic brake control i1 x i2 i3 i3 i1 i2 i1 x i2 i3 i3 i1 i2 o o i1 x i2 i3 i3 i1 i2 o 0 + + pi 6 ramp + - 3 2 data cnvst mux 2 optional current sense gate signals 3 encoder a/b/z encoder hall a/b/c motor phase current v motor phase current w current offset w current offset v id scale iq scale 4096 4096 vdlim - vdlim curkp curki - vqlim vqlim idref int_ref velocity control enable reference select feedforward path enable slip gain enable enctype accel rate decel rate 4096 slip gain iqlim+ iqlim- spdkp spdki 8 channel serial a/d interface ext_ref dcv_fdbk rs232c/ rs422 interface spi slave interface start stop dir fltclr sync fault pwm active rcv snd rts cts sck sdo sdi cs 17 data address control host register interface sequence control iq id iqref vd vq vqs vds iv iw parallel interface configuration registers monitoring registers maxenccount initzval anglescale initz zpol spdscale pwmmode pwmen 2pen gsenseu gsensel modscl dtime closed loop current control update rate = pwm carrier frequency x1 or x 2 closed loop velocity control, sequencing control update rate = pwm carrier frequency / 2 communication modules optional currentsense vd enable int_vd i1 x i2 i3 i3 i1 i2 o ref scale 4096 +/-16383 = +/-max_speed int_vq +/-16383 = +/-4x of rated current for iq +/-4095 = +/-rated id for im field flux 4ch dac module int_dac1 int_dac2 int_dac3 int_dac4 dac_pwm1 dac_pwm2 dac_pwm3 dac_pwm4 figure 2. detailed block diagram of IRMCK201
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 9 input/output of IRMCK201 figure 3 shows the interface signals divi ded into sub-groups. for detailed pin assignment, please refer to table 10 in this data sheet. IRMCK201 plltest chgo lpvss csn hpwen rx tx baudsel sync hpa hpcsn hpoen sclk miso mosi hpd[0-7] redled pid[0-1] start stop ifbcal fltclr pwmactive fault sca xpd bypassmode bypassclk osc1clk sysclk pwmuh pwmul pwmvh pwmvl pwmwh pwmwl brake gatekill ifb0 ena enb enz halla hallb hallc adclk adout adcovst admux1 ressample pwm gate signal interface ir2175 interface encoder interface a/d interface host communication interface serial eeprom led discrete i/o pll & system clock ifb1 admux0 resetn osc2clk scl greenled power id figure 3. input/output of IRMCK201
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 10 host interface group signal input (i) / output (o) low (l) / high (h) true asserted function sclk i positive edge sensitive spi clock miso o - master input and slave output mosi i - master output and slave input csn i l spi chip select hpoen i l parallel data output enable hpwen i l parallel data write cycle identification hpd [7:0] i/o - parallel data hpa i h parallel data address cycle identification hpcsn i l chip select tx o - rs-232 data out rx i - rs-232 data in baudsel i h rs-232 baud rate: 0 = 57,600; 1 = 1,031,250 bps sync o l start of pwm cycle discrete i/o group signal input (i) / output (o) low (l) / high (h) true asserted function ifbcal i h current offset calibration signal start i h start command stop i h stop command fltclr i h fault clear command pwmactive o h pwm state fault o h fault state
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 11 motion peripheral group signal input (i) / output (o) low (l) / high (h) true asserted function pwmuh o pwm phase u high side pwmul o pwm phase u low side pwmvh o pwm phase v high side pwhvl o pwm phase v low side pwmwh o pwm phase w high side pwmwl o varies, based on write register 0x0d pwm phase w low side brake o l igbt gate gatekill i varies, based on write register 0x0c bit 7 when asserted, negates all six pwm signals, host writeable ifb0 i - channel 0 (phase v) ifb1 i - channel 1 (phase w) ena i - encoder a enb i - encoder b enz i - encoder z halla i - hall a hallb i - hall b hallc i - hall c analog interface group signal input (i) / output (o) low (l) / high (h) true asserted function adclk o negative edge sensitive clock to ads7818 adout i - serial data from ads7818 dac [3:0] o - diagnostic dac adconvst o l conversion start to ads7818 admux0 o h analog input mux select admux1 o h analog input mux select
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 12 pll interface group signal input (i) / output (o) low (l) / high (h) true asserted function xpd i l pll reset resetn i l digital logic reset bypassclk i h internal test pin ? force to logic low bypassmode i h internal test pin ? force to logic low osc1clk i - 33.33 mhz crystal input osc2clk i - 33.33 mhz crystal input plltest i h internal test pin ? force to logic low chgo i/o - low pass filter lpvss i/o - low pass filter ground miscellaneous group signal input (i) / output (o) low (l) / high (h) true asserted function sd o varies, based on write register 0x0c bit 1 shut down, host writeable sca i/o - eeprom data scl o positive edge sensitive eeprom clock pid[0:1] i - power id to systemstatus register, host readable greenled o h led signal redled o h led signal power supply group signal function lvdd ic logic +3.3v power supply avcc ic analog +3.3v power supply mvdd ic phase +3.3v lock loop power supply vsshc ic phase lock loop power supply return
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 13 typical application connections typical application connection is shown in figure 4. in or der to complete a high performance servo drive control, all necessary components are shown in connection to IRMCK201. IRMCK201 tx rx start stop ifbcal fltclr pwmactive sync sca parallel data control signals scl redled greenled pid[0-1] sclk miso mosi csn sysclk pwmuh pwmul pwmvh pwmvl pwmwh pwmwl brake gatekill ifb0 ena enb enz halla hallb hallc adclk adout adconvst admux0 ressample motor current sensing encoder interface to pc rs232c optional microcontroller input switches serial eeprom bi-color led system clock ir2175 ir2175 ads7818 4052 1/4 4066 ds3486 ifb1 ds3486 ds3486 1/4 4066 admux1 po po 5v 5v 5v 33mhz crystal isolator isolator isolator isolator isolator isolator isolator isolator isolator isolator faultclr isolator spi interface max232a 8051 up at24c01a anaog reference input dc bus voltage optional current sensing optional current sensing dac0 dac1 dac2 dac3 analog output baudsel gate drive or intelligent igbt power module (iramx16up60a) figure 4. typical connection of IRMCK201
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 14 ic crystal clock circuitry the clock input to the ic is a 33.33 mhz crystal oscillator. two shunt capacitors and po ssibly a series resistor is required to terminate the crystal to the ic. the values of the r/c will vary based on actual pcb attributes, and some empirical analysis may be required to get the pll to start oscillating. once oscillating, verify that the signal waveforms at the osc1clk and osc2clk pins are sinusoidal rather than trapezoidal. refer to table 1 for sugge sted r/c values. most low-cost crystals can be used in this application. an example is a citizen part number cm309b33.333mabjt available from digi-key under part number 300-4160-1-nd. osc1clk osc2clk c1 IRMCK201 c2 r1 xtal r2 figure 5. oscillator circuit component value units xtal 33.33 mhz c1 5 pf c2 5 pf r1 0 ? r2 3.9k ? table 1: typical values for the clock circuit
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 15 pll clock circuitry the IRMCK201 contains a pll that creates a 2x and 4x clock from the input 33.33 mhz input clock pin. there are a number of pins on the ic allocated for factory testing purposes, which need to be left unconnected. table 2 shows required pcb signal connections for these pins. note that n/c is for factory use only. pin number pcb connection 1 vss 2 vss 7 vss 15 n/c 16 n/c 17 n/c 18 n/c 23 n/c 24 n/c 25 n/c 41 n/c 45 n/c 56 n/c 89 n/c table 2: pll test pin assignments low pass filter the low pass filter for this pll resides between the chgo and lpvss pins. three passi ve components are required to implement this filter: cp, rp and cs. figur e 6 shows how to place these components around the ic. a shield should be placed below rp, cp and cs made out of copper etch. chgo lpvss rp cp cs IRMCK201 shielded by lpvss figure 6. pll low pass filter shielding
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 16 i i m m p p l l e e m m e e n n t t i i n n g g t t h h e e l l o o w w p p a a s s s s f f i i l l t t e e r r s s h h i i e e l l d d make all connections between chgo, rp, cp, cs and lpvss as short as possible. create the underlining shield by ?copper filling? a larger area in the signal plane of the pcb. connect this shie ld to the lpvss pin of the ic. do not connect this shield to signal ground (vss). c c p p r r p p a a n n d d c c s s c c o o m m p p o o n n e e n n t t v v a a l l u u e e s s for a typical fr4 pcb, the values of the passive components are shown in table 3 . component value units rp 3.9k ? cp 1000 pf cs not installed - table 3: pll low pass filter values pll reset there are two reset pins on the ic, xpd and resetn both low true. xpd holds the pll circuitry in reset when low. upon xpd going high, the pll circuitry begins to lock onto the 33.33 mhz clock input. the pll circuit may take up to 1 ms to become stable. resetn asserted low holds the internal dsp logic in reset. upon resetn going high, the ic digital logic becomes active. resetn should be held low during and at least 1 ms after xpd goes high false to hold the internal dsp logic in reset while the pll becomes stable.
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 17 dc electrical characteristics and operating conditions absolute maximum ratings note: vss = 0 volt parameter symbol limits unit s note power supply voltage vdd vss-0.3 to 4.0 v vss-0.3 to vdd+0.5 v non 5 volt tolerant pins input voltage vi vss-0.3 to 7 v only on 5 volt tolerant pins output voltage vo vss-0.3 to vdd+0.5 v output current per pin iout +/- 30 ma storage temperature tstg -65 to 150 c table 4: absolute maximum ratings recommended operating conditions note: vss = 0 volt parameter symbol min typ max units note power supply voltage vdd 3.0 3.3 3.6 v vdd v non 5 volt tolerant pins input voltage vi vss - 5.5 v only on 5 volt tolerant pins ambient temperature ta -40 - 85 c note 1 table 5: recommended operating conditions notes: 1. the ambient temperature range is recommended for tj = -40 to 125 c
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 18 dc characteristics common quiescent and leakage current parameter symbol conditions min typ max units quiescent current idds vi=vdd or vss vdd=max ioh=iol=0 ta=tj=85c - - 0.35 ua input leakage current ili vdd=max vih=vdd vil=vss -1 - 1 ua table 6: dc characteristics input characteristics ? non schmitt trigger inputs parameter symbol conditions min typ max units high level input voltage vih1 vdd=max 2.0 - - v low level input voltage vil1 vdd=min - - 0.8 v table 7: non schmitt trigger input characteristics input characteristics ? schmitt trigger inputs parameter symbol conditions min typ max units high level input voltage vt1+ vdd=max 1.1 - 2.4 v low level input voltage vt1- vdd=min 0.6 - 1.8 v hysteresis voltage vh1 vdd=min 0.1 - - v table 8: schmitt trigger input characteristics output characteristics parameter symbol conditions min typ max unit s high level output voltage voh3 vdd=min ioh=-12ma vdd - 0.4 - - v low level output voltage vol3 vdd=min ioh = 12ma - - vss + 0.4 v table 9: output characteristics
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 19 pin and i/o characteristic table pin number pin name internal ic resistor termination pin type 5.50 volt tolerant input input dc characteristic table output dc characteristic table 1 bypassmode 40k-240k pull down i - table 8 - 2 bypassclk 40k-240k pull down i - table 8 - 3 osc1clk i - - 4 lvdd p - - - 5 osc2clk o - - 6 vss p - - - 7 plltest 20k-120k pull down i - table 7 - 8 xpd i - table 7 - 9 vsshc p - - - 10 mvdd p - - - 11 vsshc p - - - 12 avdd p - - - 13 chgo o - - - 14 lpvss p - - - 15 n.c. (clki) i - table 8 - 16 n.c. (clksel) i - table 8 - 17 n.c. (cpt0) i - table 8 - 18 n.c. (cpt1) i - table 8 - 19 lvdd p - - - 20 redled o - - table 9 21 greenled o - - table 9 22 vss p - - - 23 n.c. (tstclk) i - table 8 - 24 n.c. (tstsel) i - table 8 - 25 n.c. (olap) i - table 8 - 26 pwmwl o - - table 9 27 pwmwh o - - table 9 28 pwmvl o - - table 9 29 lvdd p - - - 30 pwmvh o - - table 9 31 pwmul o - - table 9 32 vss p - - - 33 pwmuh o - table 9 34 brake o - - table 9 35 resetn 20k -120k pull up i - table 8 - 36 fltclr o - - table 9 37 gatekill 20k -120k pull up i - table 8 - 38 ifb0 i yes table 8 - 39 ifb1 i yes table 8 - 40 sd o - - table 9
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 20 pin number pin name internal ic resistor termination pin type 5.50 volt tolerant input input dc characteristic table output dc characteristic table 41 n.c. (d0) i - table 8 - 42 pid0 20k -120k pull up i - table 8 - 43 pid1 20k -120k pull up i - table 8 - 44 lvdd p - - - 45 n.c. (d3) i - table 8 - 46 csn i yes table 8 - 47 vss p - 48 mosi i yes table 8 49 miso o - - table 9 50 sclk i yes table 8 - 51 tx o - - table 9 52 rx i yes table 8 - 53 baudsel 20k -120k pull down i yes table 7 - 54 lvdd p - - - 55 admux0 o - - table 9 56 n.c. (n2) i - table 8 - 57 vss p - - - 58 admux1 o - - table 9 59 ressample o - - table 9 60 adconvst o - - table 9 61 adclk o - - table 9 62 adout i yes table 8 - 63 sync o - - table 9 64 fault o - - table 9 65 start 20k -120k pull down i yes table 8 - 66 stop 20k -120k pull down i yes table 8 - 67 ifbcal 20k -120k pull down i yes table 8 - 68 fltclr 20k -120k pull down i yes table 8 - 69 lvdd p - - - 70 pwmactive o - - table 9 71 dac[3] o - - table 9 72 vss p - - - 73 dac[2] o - - table 9 74 dac[1] o - - table 9 75 dac[0] o - - table 9 76 hpd[0] 20k -120k pull down b - table 7 table 9 77 hpd[1] 20k -120k pull down b - table 7 table 9 78 hpd[2] 20k -120k pull down b - table 7 table 9 79 vdd p - - -
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 21 pin number pin name internal ic resistor termination pin type 5.50 volt tolerant input input dc characteristic table output dc characteristic table 80 hpd[3] 20k -120k pull down b - table 7 table 9 81 hpd[4] 20k -120k pull down b - table 7 table 9 82 vss p - - - 83 hpd[5] 20k -120k pull down b - table 7 table 9 84 hpd[6] 20k -120k pull down b - table 7 table 9 85 hpd[7] 20k -120k pull down b - table 7 table 9 86 hpoen i yes table 8 - 87 hpwen i yes table 8 88 hpa i yes table 8 - 89 n.c. (n11) i - table 8 - 90 hpcsn i yes table 8 - 91 encz i yes table 8 - 92 encb i yes table 8 - 93 enca i yes table 8 - 94 lvdd p - - - 95 hallc i yes table 8 - 96 hallb i yes table 8 - 97 vss p - - 98 halla i yes table 8 - 99 scl o - - table 9 100 sda 20k -120k pull up b - table 7 table 9 table 10: pin and i/o characteristics power consumption parameter symbol conditions min typ max units p total ptotal vdd=3.3v - 0.927 - watt table 11: IRMCK201 power consumption
ac electrical characteristics and operating conditions system level ac characteristics s s y y n n c c p p u u l l s s e e t t o o s s y y n n c c p p u u l l s s e e t t i i m m i i n n g g sync speed loop current regulator sample delay space vector modulation end of processing wait for next sync pulse 0 1 2 3 4 5 678 -1 -2 -3 -4 -5 critical path timing incl uding pwm calculation time t 2 t 1 t 3 figure 7. system level sync-to-sync timing
symbol description time units t 1 current feedback sample delay from sync pulse falling edge 4.32 s closed loop computation time (current control only including pwm computation) 6.33 t 2 closed loop computation time (current and velocity control including pwm calculation time) 7.68 s minimum sync-to-sync time (current control only including pwm calculation time) 10.65 t 3 minimum sync-to-sync time (current and velocity control including pwm calculation time) 12.0 s table 12: system level sync-to-sync timing f f a a u u l l t t a a n n d d r r e e d d l l e e d d r r e e s s p p o o n n s s e e t t o o g g a a t t e e k k i i l l l l gatekill fltclr redled fault t 1 t 2 t 3 t 4 figure 8. fault and redled response to gatekill symbol description typ units t 1 fault response to gatekill 685 ns t 2 redled response to gatekill 715 ns t 3 fault response to fltclr 145 ns t 4 redled response to fltclr 175 ns table 13: fault and redled response to gatekill
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 24 host interface ac characteristics s s p p i i t t i i m m i i n n g g sclk mosi miso cs t sclk t css t mosis t misoz t miso figure 9. spi timing symbol description min max units f sclk spi clock frequency 8 mhz t sclk spi clock period 125 ns t css cs to sclk high setup 20 ns t mosis mosi to sclk low setup 20 ns t miso sclk to miso valid 30 ns t mioz cs to mosi high impedance 15 35 ns table 14: spi timing
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 25 host parallel timing h h o o s s t t p p a a r r a a l l l l e e l l r r e e a a d d c c y y c c l l e e hpwen hpd[7:0] hpoen hpa hpcsn t hpcsn valid t hpwens t hpas t hpdz t hpoen t ahpd t hpoens t hpa t hpoenh t hpzd figure 10. host parallel read cycle timing symbol description min max unit s note t hpcsn hpcsn period 70 ns t hpwens hpwens setup 10 ns t hpas hpa setup 10 ns t ahpd hpd [7:0] access 60 105 ns t hpzd hpd [7:0] active 0 9 ns t hpdz hpd [7:0] high impedance 0 6 ns t hpoenh hpoen hold 10 ns note 3 t hpoens hpoen setup 10 ns note 3 t hpoen hpoen period 70 ns table 15: host parallel read cycle timing note: 3. hpoen must be stable before and after the high to low transition of hpcsn.
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 26 h h o o s s t t p p a a r r a a l l l l e e l l w w r r i i t t e e c c y y c c l l e e hpwen hpd[7:0] hpoen hpa hpcsn t hpcsn t hpwens t hpas t hpd[7:0]s t hpoens t h p w e n t h p a t hpd[7:0] t hpoen figure 11. host parallel write cycle timing symbol description min units note t hpcsn hpcsn period 70 ns t hpwens hpwens setup 10 ns t hpwen hpwen period 70 ns t hpas hpa setup -10 ns t hpa hpa period 70 ns t hpd[7:0] hpd[7:0] setup -10 ns t hpoens hpoen setup 10 ns t hpoen hpoen period 70 ns note 4 table 16: host parallel write cycle timing note: 4. hpoen must be asserted high while hpcs n low during a host parallel write cycle.
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 27 discrete i/o electrical characteristics ifbcal start stop fltclr gatekill t l figure 12. discrete i/o timing symbol description min units t l pulse width ifbcal 100 ms pulse width start 100 ns pulse width stop 100 ns pulse width fltclr 1 us pulse width gatekill 490 ns table 17: discrete i/o timing
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 28 motion peripheral electrical characteristics p p w w m m e e l l e e c c t t r r i i c c a a l l c c h h a a r r a a c c t t e e r r i i s s t t i i c c s s sync pwmuh pwmul pwmvh pwmvl pwmwh pwmwl t deadtimeresolution t deadtimeresolution figure 13. pwm timing symbol description value units t deadtimeresolution deadtime insertion logic resolution 30 ns table 18: pwm timing i i r r 2 2 1 1 7 7 5 5 i i n n t t e e r r f f a a c c e e ifb0 ifb1 t ifb t ifbl t ifbh figure 14. ir2175 interface symbol description min max units f ifb current feedback input frequency 95 165 khz t ifb current feedback period 10.52 6.06 s t ibh current feedback high pulse width 500 ns 10 us t ifbh current feedback low pulse width 500 ns 10 us table 19: ir2175 interface
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 29 e e n n c c o o d d e e r r e e l l e e c c t t r r i i c c a a l l c c h h a a r r a a c c t t e e r r i i s s t t i i c c s s table 20 shows the input timing characteristics of the encoder inputs. please refer to the IRMCK201 application developer?s guide for an example encoder input circuit that drives the IRMCK201. ena enb enz halla hallb hallc resetn t encoder t encl t ench t hallabcs valid figure 15. encoder timing symbol description min typ max units f encoder encoder input frequency 1 mhz t encoder ena enb enz period 1 s t encl ena enb enz pulse width 500 ns t ench ena enb enz pulse width 500 ns t hallabcs halla hallb hallc setup to resetn 1 s table 20: encoder timing
analog to digital interface electrical characteristics a a d d c c t t i i m m i i n n g g system level timing the IRMCK201 contains logic to drive an adc converter, analog mux and associated sample and hold circuits. figure 16 and table 21 show the system level timing of these elements. figure 17 and table 22 show specific timing parameters associated with the adc converter. ref er to the application developers guide for a detailed description of adc, mux and sample and hold signal system level protocol. the IRMCK201 adc int erface has been designed for interfacing to the burr-brown ads7818 adc and texas instruments cd4052 mux. sync adconvst ressample admux0 admux1 adclk t adclk t adclk t sync t adconvst t admux1s t admux figure 16. top level adc timing symbol description min typ max units t sync sync pulse width 3 s t ressamples sync falling edge to ressample valid -10 10 ns t admux0s adconvst to admux0 valid 40 61 ns t admux1s adconvst to admux1 valid 40 61 ns t adconvsts adconvst to adclk 71 91 ns table 21: top level adc timing
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 31 converter level timing adclk adconvst ressample adout t adclk admux0 admux1 t hadout t adouts d11 d10 d2 d1 d0 t 2 t 3 t 1 figure 17. adc specific timing symbol description value min max units f adclk adc clock frequency 8.33 mhz t adclk adc clock period 120 ns t 1 ressample to adclk 91 ns t 2 ressample to adconvst 40 ns t 3 ressample to admux0, admux1 64 ns t hadout adout to adclk setup 19.7 t adouts adout to adclk hold 2 ns table 22: adc specific timing
pll interface electrical characteristics parameter symbol condition s min typ max units current consumption idds static - - 170 a current consumption idd dynamic - 5 - ma peak jitter tpj - - - 1000 ps cycle jitter tcj - -500 - +500 ps lock-up time tlock - - - 1 ms pll reset period trst recommended operating condition 10 - - ns table 23: pll electrical characteristics
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 33 appendix a host register map a host computer controls the IRMCK201 using its slave-mode full-duplex spi port, a standard rs-232 port or a 8-bit parallel port for connection to a micropro cessor. all interfaces are always ac tive and can be used interchangeably, although not simultaneously. control/status registers are mappe d into a 128-byte address space. h h o o s s t t p p a a r r a a l l l l e e l l a a c c c c e e s s s s the IRMCK201 contains an address register that is updated w ith the host register address that all subsequent data transfers are to access. this address register is updated during host parallel write cycles where the hpa signal is asserted to a logical high. the di agram below shows that data bytes 0 to n would access the register location specified by the address byte. the address bye w ith the hpa signal can be asserted at any time. address byte hpa = 1 data byte 0 hpa = 0 ?????. hpa = 0 data byte n hpa = 0 host parallel data transfer format s s p p i i r r e e g g i i s s t t e e r r a a c c c c e e s s s s when configured as an spi device read only and read/wr ite operations are performed using the following transfer format: command byte data byte 0 ?????. data byte n data transfer format bit position 7 6 5 4 3 2 1 0 read only register map starting address command byte format data transfers begin at the address specified in the command byte and pro ceed sequentially until the spi transfer completes. note that accesses are read/w rite unless the ?read only? bit is set. r r s s - - 2 2 3 3 2 2 r r e e g g i i s s t t e e r r a a c c c c e e s s s s the IRMCK201 includes an rs-232 interface channel that allows operation using a direct connection to the host pc. this interface implements a simple protoc ol that checks the validity of data prio r to being written into a register. the protocol is explained below. rs-232 register write access a register write operation consists of a command/address by te, byte count, register data and checksum. when the IRMCK201 receives the register data, it validates the ch ecksum, writes the register data, and transmits and acknowledgement to the host.
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 34 command / address byte byte count 1-6 bytes of register data checksum register write operation command acknowledgement byte checksum register write acknowledgement bit position 7 6 5 4 3 2 1 0 1=read/ 0=write register map starting address command/address byte format bit position 7 6 5 4 3 2 1 0 1=error/ 0=ok register map starting address command acknowledgement byte format the following example shows a command sequence sent from the host to the irmco201 requesting a two-byte register write operation: 0x2f write operation beginning at offset 0x2f 0x02 byte count of register data is 2 0x00 data byte 1 0x04 data byte 2 0x35 checksum (sum of preceding bytes, overflow discarded) a good reply from the IRMCK201 would appear as follows: 0x2f write completed ok at offset 0x2f 0x2f checksum an error reply to the command would have the following format: 0xaf write at offset 0x2f completed in error 0xaf checksum rs-232 register read access a register read operation consists of a command/address byte, byte count and checksum. when the IRMCK201 receives the command, it validates the checksum and transmits the register data to the host.
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 35 command / address byte byte count checksum register read operation command acknowledgement byte register data (byte count bytes) checksum register read acknowledgement (transfer ok) command acknowledgement byte checksum register read acknowledgement (error) the following example shows a command sequence sent from the host to the IRMCK201 requesting four bytes of read register data: 0xa0 read operation beginning at offset 0x20 (high-order bit selects read operation) 0x04 requested data byte count is 4 0xa4 checksum a good reply from the IRMCK201 might appear as follows: 0x20 read completed ok at offset 0x20 0x11 data byte 1 0x22 data byte 2 0x33 data byte 3 0x44 data byte 4 0xca checksum an error reply to the command would have the following format: 0xa0 read at offset 0x20 completed in error 0xa0 checksum rs-232 timeout the IRMCK201 receiver includes a timer th at automatically terminates transfer s from the host to the IRMCK201 after a period of 32 msec. rs-232 transfer examples the following example shows a normal exch ange executing a register write access.
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 36 the example below shows a normal register read access exchange. the following example shows a register write request that is repeated by the host due to a negative acknowledgement from the IRMCK201. in the final example, the host repeats a register read access request when it r eceives no response to its first attempt.
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 37
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 38 write register definitions q q u u a a d d r r a a t t u u r r e e d d e e c c o o d d e e r r e e g g i i s s t t e e r r g g r r o o u u p p ( ( w w r r i i t t e e r r e e g g i i s s t t e e r r s s ) ) byte offset bit position 7 6 5 4 3 2 1 0 0x0 enccntw (lsbs) (w) 0x1 enccntw (msbs) (w) 0x3 maxenccnt (lsbs) (w) 0x4 maxenccnt (msbs) (w) 0x6 zenccnt (lsbs) (w) 0x7 zenccnt (msbs) (w) 0x9 encangscl (lsbs) (w) 0xa encangscl (msbs) (w) 0xb spare redsig (w) pwron redsig (w) zpulse enb (w) zpulsepol (w) cntenb (w) quadraturedecode write register map field name access (r/w) field description enccntw w new value for 16-bit quadrature decoder counter. maxenccnt w maximum value of 16-bit quadrature decoder counter. the encoder count is reset to 0 a fter this count has been reached. this maximum should be set to correspond to a 360-degree physical angle. zenccnt w encoder count value when the z- pulse occurs. this value is loaded automatically in hardware when the z-pulse occurs. (see zpulseenb and zpulsepol fields below.)
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 39 field name access (r/w) field description encangscl w this value should be set to ((mtrpoles / 2) * (4096 * 4096) / (maxenccnt + 1), where mtrpol es is the number of motor poles. the value is used to c onvert the encoder count to an angle ranging from 0 - 4095 using the equation: angle = ((mtrpoles / 2) * 4096 * (encoder count) / (maxenccnt + 1)) mod 4096. (the current encoder count can be read from the enccntr feld of the quadraturedecodestatus read register group.) cntenb w encoder counter enable. zpulsepol w zpulse polarity. 1= load zenccnt on rising z-pulse edge. 0= load zenccnt on falling z-pulse edge. zpulseenb w zpulse count initialization enable. when this bit is set, the encoder count is set to the zenccnt value at each z-pulse edge as determined by the zpulsepol field. pwronredsig w poweron reduced signal enable. set this bit in the eeprom to enable eeprom standalone initialization for a wire-saving encoder. when this bit is set, the eeprom initialization uses the pwronh alla, pwronhallb, pwronhallc bits instead of the halla, hallb, hallc bits to determine initial motor angle. (the hall bits can be read from the quadraturedecodestatus read register group.) redsig w reduced signal encoder enable. 1 = read hall a/b/c fields from encoder a/b/z wires. quadraturedecode write register field definitions p p w w m m c c o o n n f f i i g g r r e e g g i i s s t t e e r r g g r r o o u u p p ( ( w w r r i i t t e e r r e e g g i i s s t t e e r r s s ) ) byte offset bit position 7 6 5 4 3 2 1 0 0xc gatekill sns (w) spare gate snsl (w) gate snsu (w) spare sd (w) spare 0xd pwmperiod (lsbs) (w) 0xe spare pwmconfig (w) pwmperiod (msbs) (w) 0xf pwmdeadtm (w) pwmconfig write register map
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 40 field name access (r/w) field description sd w shutdown control output to ir213x. gatesnsu w upper igbt gate sense. 1 = active high gate control, 0 = active low gate control. gatesnsl w lower igbt gate sense. 1 = active high gate control, 0 = active low gate control. gatekillsns w gatekill signal sense. 1 = active high gatekill, 0 = active low gatekill. pwmperiod w this field is used to set the desired pwm frequency using the following equation: pwmperiod = 33,333,000 / ( 2 * (pwm frequency)) ? 1, where 33,333,000 is the system clock frequency (33.333mhz). note that while "pwmperiod" is t he name of this field, the actual pwm carrier period is 2 * (pwmperiod + 1) * (system clock period = 30ns). pwmconfig w pwm configuration. 0 = as ymmetrical center aligned pwm, 1 = symmetrical center aligned pwm. pwmdeadtm w gate drive dead time in units of system clock cycles (e.g., 30 ns with 33 mhz clock). pwmconfig write register field definitions c c u u r r r r e e n n t t f f e e e e d d b b a a c c k k c c o o n n f f i i g g r r e e g g i i s s t t e e r r g g r r o o u u p p ( ( w w r r i i t t e e r r e e g g i i s s t t e e r r s s ) ) byte offset bit position 7 6 5 4 3 2 1 0 0x10 ifboffsv (lsbs) (w) 0x11 ifboffsw (lsbs) (w) ifboffsv (msbs) (w) 0x12 ifboffsw (msbs) (w) 0x13 idscl (lsb) (w) 0x14 idscl (msb) (w) 0x15 iqscl (lsb) (w) 0x16 iqscl (msb) (w) currentfeedbackconfig write register map
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 41 field name access (r/w) field description ifboffsv w 12-bit signed value for v phase current feedback offset. when the ifboffsenb bit in the systemcontrol write register group is "0" this value is automatically added to each current measurement in hardware. ifboffsw w 12-bit signed value for w phase current feedback offset. when the ifboffsenb bit in the systemcontrol write register group is "0? this value is automatically added to each current measurement in hardware. idscl w rotating frame id component current feedback scale factor. constant used to scale current measurements before they are used in the field orientation calculation. this is a 15-bit fixed-point signed number with 10 fractional bits that ranges from ?16 to + 16 + 1023 / 1024. iqscl w rotating frame iq component current feedback scale factor. constant used to scale current measurements before they are used in the field orientation calculation. this is a 15-bit fixed-point signed number with 10 fractional bits that ranges from ?16 to + 16 + 1023 / 1024. currentfeedbackconfig write register field definitions s s y y s s t t e e m m c c o o n n t t r r o o l l r r e e g g i i s s t t e e r r g g r r o o u u p p ( ( w w r r i i t t e e r r e e g g i i s s t t e e r r s s ) ) byte offset bit position 7 6 5 4 3 2 1 0 0x17 dccomp enb ifboffs enb spare reserved foc enbw pwm enbw systemcontrol write register map field name access (r/w) field description pwmenbw w pwm enable bit. setting this bit to 1 or 0 sets the igbt gate control signals to their active or inactive states. at power up the gate control output signals remain in a high-z stat e. after pwmenbw is set for the first time, the gate controls are driven to their active or inactive states according to the value of pwmenbw. a fault condition clears this bit automatically in hardware. focenbw w field orientated control enable bit. setting this bit to 1 enables the foc algorithm. setting this bit to 0 resets the foc algorithm and causes zero output voltage to be applied to the motor. a fault condition clears this bit automatically in hardware. reserved w this field should is reserved and should be set to 0.
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 42 field name access (r/w) field description ifboffsenb w when ifb pwmenbw = 1, and foce nbw = 0, the current feedback offset is calculated and saved in the currentfeedbackoffset read register group. when ifboffsenb = 1, the current feedback offset values in the currentfeedbackoffset read registers are applied to each current feedback measurement. when ifboffsenb = 0, the current feedback offset values in the currentfeedbackconfig write registers are applied to each current feedback measurement. dccompenb w dc bus compensation enable. when this bit is set to "1", pwm output is compensated for using the following formula: pwm (comp) = pwm * 310 / dcbusvolts where pwm (comp) is the com pensated pwm output voltage; pwm is the uncompensated pwm output voltage; 310 is the nominal dc bus voltage; and dcbusvolts is the actual dc bus voltage. systemcontrol write register field definitions c c u u r r r r e e n n t t l l o o o o p p c c o o n n f f i i g g r r e e g g i i s s t t e e r r g g r r o o u u p p ( ( w w r r i i t t e e r r e e g g i i s s t t e e r r s s ) ) byte offset bit position 7 6 5 4 3 2 1 0 0x18 iqrefw ? quadrature reference current (lsbs) (w) 0x19 iqrefw ? quadrature reference current (msbs) (w) 0x1a kpireg ? current loop proportional gain (lsbs) (w) 0x1b kpireg ? current loop proportional gain (msbs) (w) 0x1c kxireg ? current loop integral gain (lsbs) (w) 0x1d kxireg ? current loop integral gain (msbs) (w) 0x1e idref ? direct/magnetizing re ference current (lsbs) (w) 0x1f idref ? direct/magnetizing reference current (msbs) (w) 0x20 slipgn (lsbs) (w) 0x21 slipgn (msbs) (w) 0x22 vqlim ? quadrature current output limit (lsbs) (w) 0x23 vqlim ? quadrature current output limit (msbs) (w)
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 43 byte offset bit position 7 6 5 4 3 2 1 0 0x26 vdlim ? direct current output limit (lsbs) (w) 0x27 vdlim ? direct current output limit (msbs) (w) currentloopconfig write register map field name access (r/w) field description iqrefw w 15-bit signed quadrature current re ference input from velocity loop. kpireg w 15-bit signed current loop pi controller proportional gain. scaled with 14 fractional bits for an effective range of 0 ? 1. kxireg w 15-bit signed current loop pi cont roller integral gain. scaled with 19 fractional bits for an effective range of 0 - .03125. idref w 15-bit signed direct/magnetized current to d-axis current loop pi controller. slipgn w this parameter controls the slip speed for induction motor applications. slipgn should be set to 2048 * 2048 * (rated slip speed in hz) / (current loop update frequency). slipgn must be set to 0 if slip is not desired. vqlim w 16-bit quadrature current pi controller voltage output limit. vdlim w 16-bit direct current pi controller voltage output limit. currentloopconfig write register field definitions v v e e l l o o c c i i t t y y c c o o n n t t r r o o l l r r e e g g i i s s t t e e r r g g r r o o u u p p ( ( w w r r i i t t e e r r e e g g i i s s t t e e r r s s ) ) byte offset bit position 7 6 5 4 3 2 1 0 0x31 spare spdlprate spdlpenb 0x32 kpsreg ? velocity loop proportional gain (lsbs) (w) 0x33 kpsreg ? velocity loop proportional gain (msbs) (w) 0x34 kxsreg ? velocity loop integral gain (lsbs) (w) 0x35 kxsreg ? velocity loop integral gain (msbs) (w) 0x36 sreglimp ? velocity l oop positive limit (lsbs) (w) 0x37 sreglimp ? velocity l oop positive limit (msbs) (w)
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 44 byte offset bit position 7 6 5 4 3 2 1 0 0x38 sreglimn ? velocity loop negative limit (lsbs) (w) 0x39 sreglimn ? velocity loop negative limit (msbs) (w) 0x3a spdscl ? speed scale factor (lsbs) 0x3b spdscl ? speed scale factor (msbs) 0x3c targetspd ? setpoint/target speed (lsbs) 0x3d targetspd ? setpoint/target speed (msbs) 0x3e spdaccrate ? acceleration 0x3f spddecrate ? deceleration velocitycontrol write register map field name access (r/w) field description spdlpenb w speed loop enable: 1 = enable s peed loop pi controller. 0 = reset speed loop pi controller. spdlprate w speed loop update rate: 0 = disabled, n = update speed loop immediately before every nth current loop update. kpsreg w 15-bit velocity loop proportional gain, in fixed point with 5 fractional bits. range = 0 - 512. kxsreg w 15-bit velocity loop integral gain, in fixed point with 13 fractional bits. range = 0 - 2. sreglimp w 16-bit speed pi controller output positive limit. sreglimn w 16-bit speed pi controller out put negative limit (2's complement). spdscl w motor speed scale factor. the user should set spdscl = 60 * 16383 * (33.333mhz/32) / (max rpm * encoder ppr) / 2, which will result in a speed value ranging 16384 corresponding to max rpm. targetspd w velocity loop speed setpoi nt in speed units, which are determined by the user via the spdscl register setting. spdaccrate w velocity loop acceleration in units of speed / velocity loop execution or speed / (spdlprate / pwm period). spddecrate w velocity loop deceleration in units of speed / velocity loop execution or speed / (spdlprate / pwm period). velocitycontrol write register field definitions
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 45 f f a a u u l l t t c c o o n n t t r r o o l l r r e e g g i i s s t t e e r r g g r r o o u u p p ( ( w w r r i i t t e e r r e e g g i i s s t t e e r r s s ) ) byte offset bit position 7 6 5 4 3 2 1 0 0x42 spare fltclr dcbusm enb faultcontrol write register map field name access (r/w) field description dcbusmenb w dc bus monitor enable. 1 = monitor dc bus voltage and generate appropriate brake signal control and disable pwm output when voltage fault conditions occur. gatekillflt and ovrspdflt faults cannot be disabled. dc bus volt age thresholds are as follows: overvoltage ? 410v brake on ? 380v brake off ? 360v nominal ? 310v undervoltage off ? 140v undervoltage ? 120v fltclr w this bit clears all active fault c onditions. the user should monitor the faultstatus read register group to determine fault status and set this bit to ?1? to clear any faults that have occurred. a fault condition automatically clears the pwme nbw and focenbw bits in the systemcontrol write register group. no te that this bit also directly controls the output 2137 fltclr pin. after clearing a fault, the user must explicitly set this bit to ?0? to re-enable fault processing. faultcontrol write register field definitions s s v v p p w w m m s s c c a a l l e e r r r r e e g g i i s s t t e e r r g g r r o o u u p p ( ( w w r r i i t t e e r r e e g g i i s s t t e e r r s s ) ) byte offset bit position 7 6 5 4 3 2 1 0 0x44 modscl (lsbs) (w) 0x45 modscl (msbs) (w) svpwmscaler write register map
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 46 field name access (r/w) field description modscl w space vector modulator scale factor. this register, which depends on the pwm carrier frequency, should be set as follows: modscl = pwmperiod * sqrt(3) * 4096 / 2355 where pwmperiod is the value in the pwmconfig write register group?s pwmperiod register. svpwmscaler write register field definitions d d i i a a g g n n o o s s t t i i c c p p w w m m c c o o n n t t r r o o l l r r e e g g i i s s t t e e r r g g r r o o u u p p ( ( w w r r i i t t e e r r e e g g i i s s t t e e r r s s ) ) byte offset bit position 7 6 5 4 3 2 1 0 0x4e pwmdata1sel pwmdata0sel 0x4f pwmdata3sel pwmdata2sel diagnosticpwmcontrol write register map field name access (r/w) field description pwmdata0sel, pwmdata1sel, pwmdata2sel, pwmdata3sel w selects diagnostic data items for output on dac pwm pins 0-3. these pins are intended for use with external rc filters for oscilloscope diagnostic display: 1 = dc bus voltage 2 = v phase current 3 = w phase current 5 = speed pi reference 6 = speed pi feedback 7 = speed pi error 8 = iq ref 9 = q axis voltage qv 10 = d axis voltage dv 11 = 12-bit electrical angle 12 = q axis current qi 13 = d axis current di 14 = a axis (stationary frame) voltage av 15 = b axis (stationary frame) voltage bv diagnosticpwmcontrol write re gister field definitions
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 47 s s y y s s t t e e m m c c o o n n f f i i g g r r e e g g i i s s t t e e r r g g r r o o u u p p ( ( w w r r i i t t e e r r e e g g i i s s t t e e r r s s ) ) byte offset bit position 7 6 5 4 3 2 1 0 0x50 extctrlw spdrefsel iqrefsel hostang enb hostvd enb rmpref sel systemconfig write register map field name access (r/w) field description rmprefsel w speed ramp reference select. 0= targetspd field of the velocitycontrol write register gr oup, 1 = external analog reference. hostvdenb w host d-axis current control enable. when this bit is set, the d-axis pi controller is disconnected from the forward path vector rotator, which then takes its input from the vdsfwd field of the directhostvoltagecontrol write register group. hostangenb w host electrical angle control enable. when this bit is set, the vector rotator takes its angle input from the elecangw field of the directhostvoltagecontrol write register group. iqrefsel w selects the source for the q-axis pi controller iqref input: 0 = speed pi controller output 1 = iqrefw field of the currentloopconfig write register group 2 = reference a/d converter input. spdrefsel w selects the source for the speed pi controller reference input: 0 = internal accel/deccel ramp generator 1 = targetspd field of the velo citycontrol write register group 2 = reference a/d converter input. extctrlw w setting this bit to ?1? enables direct control of basic motor operation via the external user interface pi ns. when this bit is ?1?, the focenbw and pwmenbw bits in the systemcontrol write register group are ignored. systemconfig write register field definitions d d i i r r e e c c t t h h o o s s t t v v o o l l t t a a g g e e c c o o n n t t r r o o l l r r e e g g i i s s t t e e r r g g r r o o u u p p ( ( w w r r i i t t e e r r e e g g i i s s t t e e r r s s ) ) byte offset bit position 7 6 5 4 3 2 1 0 0x52 vdsfwd (lsbs) (w) 0x53 vqsfwd (lsbs) (w) vdsfwd (msbs) (w)
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 48 byte offset bit position 7 6 5 4 3 2 1 0 0x54 vqsfwd (msbs) (w) 0x55 elecangw (lsbs) (w) 0x56 spare elecangw (msbs) (w) directhostvoltage control write register map field name access (r/w) field description vdsfwd w 12-bit signed value for synchronous frame direct current when host direct current control is enabled. this field is typically used for v/hz control. vqsfwd w 12-bit signed value for synchronous frame quadrature voltage that is added to the q-ax is pi-controller output. this field is typically used for f eedforward or v/hz control. elecangw w 12-bit electrical angle used when host electrical angle control is enabled. this field is typi cally used for v/hz control. directhostvoltagecontrol write register field definitions 3 3 2 2 b b i i t t q q u u a a d d d d e e c c o o d d e e r r e e g g i i s s t t e e r r g g r r o o u u p p ( ( w w r r i i t t e e r r e e g g i i s s t t e e r r s s ) ) byte offset bit position 7 6 5 4 3 2 1 0 0x58 enccnt32bw (bits 0-7) (w) 0x59 enccnt32bw (bits 8-15) (w) 0x5a enccnt32bw (bits 16-23) (w) 0x5b enccnt32bw (bits 24-31) (w) 32bitquaddecode write register map field name access (r/w) field description enccnt32bw w new value for 32-bit quadrature decoder counter. 32bitquaddecode write register field definitions
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 49 e e e e p p r r o o m m c c o o n n t t r r o o l l r r e e g g i i s s t t e e r r s s ( ( w w r r i i t t e e r r e e g g i i s s t t e e r r s s ) ) at power up, the write registers can be optionally initiali zed with values stored in eeprom. the eepromcontrol write register group and eepromstatus read register group are used to read and write these eeprom values. since the eeaddrw write register (which selects the eeprom offs et to read or write) does not require initialization at power up, the location corresponding to that register in eeprom (at offset 0x5d) is used to store a register map version code. at power on, the fpga initializes the write registers from eeprom only if the version code stored at this offset in eeprom matches its internal register map version code (which can be read from the regmapver field of the eepromstatus read register group). to enable write register initialization at power up, write the appropriate register map version code to eeprom at offset 0x5d. to disable write register initialization at power up, write a zer o (or any non-matching version code) to offset 0x5d of the eeprom. byte offset bit position 7 6 5 4 3 2 1 0 0x5c spare eewrite eeread eerst 0x5d eeaddrw / regmapverscode (w) 0x5e eedataw (w) eepromcontrol write register map field name access (r/w) field description eerst w self-clearing eeprom reset. writing a "1" to this bit resets the i2c eeprom interface. eeread w self-clearing i2c eeprom read. writing a "1" to this bit initiates an eeprom read from the byte located at eeprom address eeaddrw. after setting this bit the user should poll the eebusy bit in the eepromstatus read register group to determine when the read completes and then read the data from eedatar in the eepromstatus read register group. eewrite w self-clearing eeprom write. writing a "1" to this bit initiates an eeprom write from the data byte in eedataw to the eeprom address eeaddrw. eeaddrw w eeprom address register. contains the address for the next eeprom read or write operation. eedataw w eeprom data register. contains the data for the next eeprom write operation. eepromcontrol write register field definitions
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 50 h h a a l l l l s s e e n n s s o o r r e e n n c c o o d d e e r r i i n n i i t t ( ( w w r r i i t t e e r r e e g g i i s s t t e e r r s s ? ? e e e e p p r r o o m m o o n n l l y y ) ) these values must be set in the eep rom for initial encoder count/angle initiali zation in the eeprom standalone (i.e. operation without a host program). eepro m initialization logic automatically lo ads the appropriate value into the encoder counter at power-on based on the hall a/b/c sens or values. these values are present only in the eeprom since they serve no purpose after power on. byte offset bit position 7 6 5 4 3 2 1 0 0x72 hallcba001(lsbs) 0x73 hallcba001(msbs) 0x74 hallcba010 (lsbs) 0x75 hallcba010 (msbs) 0x76 hallcba011(lsbs) 0x77 hallcba011(msbs) 0x78 hallcba100 (lsbs) 0x79 hallcba100 (msbs) 0x7a hallcba101(lsbs) 0x7b hallcba101(msbs) 0x7c hallcba110 (lsbs) 0x7d hallcba 110 (msbs) hallsensorencoderinit register map field name access (r/w) field description hallcba nnn w (eeprom only) initial encoder count for hall sensor [c, b, a] value [ n , n , n ]. hallsensorencoderinit field definitions
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 51 read register definitions q q u u a a d d r r a a t t u u r r e e d d e e c c o o d d e e s s t t a a t t u u s s r r e e g g i i s s t t e e r r g g r r o o u u p p ( ( r r e e a a d d r r e e g g i i s s t t e e r r s s ) ) byte offset bit position 7 6 5 4 3 2 1 0 0x0 enccntr (lsbs) (r) 0x1 enccntr (msbs) (r) 0x3 spare pwron hallc pwron hallb pwron halla spare hallc hallb halla quadraturedecodestatus read register map field name access (r/w) field description enccntr r current value of 16-bit quadrature decoder counter. halla, hallb, hallc r hall sensor a/b/c values. pwronhalla, pwronhallb, pwronhallc r hall sensor a/b/c values at power-on for reduced-wire encoder interface. quadraturedecodestatus read register field definitions s s y y s s t t e e m m s s t t a a t t u u s s r r e e g g i i s s t t e e r r g g r r o o u u p p ( ( r r e e a a d d r r e e g g i i s s t t e e r r s s ) ) byte offset bit position 7 6 5 4 3 2 1 0 0x7 start stop spare pwrid gatekill foc enbr pwm enbr 0x8 revcode (lsbs) 0x9 revcode (msbs) systemstatus read register map
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 52 field name access (r/w) field description pwmenbr r pwm enable bit status. focenbr r foc enable bit status. gatekill r gatekill status. this bit is set by the gatekill input from the ir2137. once set, this bit remains set until it is cleared by writing a ?1? to the faultclr bit in the faultcontrol write register group. pwrid r power id. 0 = 3 kw, 1 = 2 kw, 2 = 500 w. stop r user interface "stop" digital input status. start r user interface "start" digital input status. revcode r ic revision code. revision c ode format is ?xx.xx?, where each ?x? is a 4-bit hexadecimal number. systemstatus read register field definitions d d c c b b u u s s v v o o l l t t a a g g e e r r e e g g i i s s t t e e r r g g r r o o u u p p ( ( r r e e a a d d r r e e g g i i s s t t e e r r s s ) ) byte offset bit position 7 6 5 4 3 2 1 0 0xa dcbusvolts (lsbs) 0xb spare brake dcbusvolts (msbs) dcbusvoltage read register map field name access (r/w) field description dcbusvolts r dc bus voltage. data range is 0 - 4095, which corresponds to a dc bus voltage between 0 and 500 volts. brake r brake signal status. 0 = brake signal active. dcbusvoltage read regi ster field definitions f f o o c c d d i i a a g g n n o o s s t t i i c c d d a a t t a a r r e e g g i i s s t t e e r r g g r r o o u u p p ( ( r r e e a a d d r r e e g g i i s s t t e e r r s s ) ) byte offset bit position 7 6 5 4 3 2 1 0 0xc ivfbk - v phase ifb raw current (lsbs) (r) 0xd iwfbk - w phase ifb raw current (lsbs) (r) ivfbk - v phase ifb raw current (msbs) (r)
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 53 byte offset bit position 7 6 5 4 3 2 1 0 0xe iwfbk - w phase ifb raw current (msbs) (r) 0xf id ? synchronous frame direct current (lsbs) (r) 0x10 id ? synchronous frame direct current (msbs) (r) 0x11 iq ? synchronous frame quadrature current (lsbs) (r) 0x12 iq ? synchronous frame quadrature current (msbs) (r) 0x13 ud ? synchronous frame direct voltage (lsbs) (r) 0x14 ud ? synchronous frame direct voltage (msbs) (r) 0x15 uq ? synchronous frame quadrature voltage (lsbs) (r) 0x16 uq ? synchronous frame quadrature voltage (msbs) (r) 0x17 ualpha ? stationary frame alpha voltage (lsbs) (r) 0x18 ubeta ? stationary frame beta voltage (lsbs) (r) ualpha ? stationary frame alpha voltage (msbs) (r) 0x19 ubeta ? stationary frame beta voltage (msbs) (r) focdiagnosticdata read register map field name access (r/w) field description ivfbk, iwfbk r offset-corrected v and w phase raw current from the ir2175 current sensor. values range from 0 - 4096, where 2048 corresponds to 0 current. the current feedback scale factors idscl and iqscl in the currentfeedbackconfig write regist er group and the current sense resistor value determine the full scale current value. id, iq r synchronous or rotating frame direct and quadrature current values in 2?s complement representation. the full scale current values range from ?16384 to 16383. ud, uq r synchronous or rotating frame direct and quadrature voltage values in 2?s complement representation. data ranges are vdlim for ud and vqlim for uq as specifi ed in the currentloopconfig write register group.
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 54 ualpha, ubeta r stationary frame alpha and beta voltage output component values. data range is vdlim or vqlim (as specified in the currentloopconfig write register group), whichever is larger. focdiagnosticdata read regi ster field definitions f f a a u u l l t t s s t t a a t t u u s s r r e e g g i i s s t t e e r r g g r r o o u u p p ( ( r r e e a a d d r r e e g g i i s s t t e e r r s s ) ) the fault status register records fault conditions that occur during drive operation. when any of these fault conditions occur, the pwm output is automatically disabled. the user should monitor this register continuously for fault conditions. a fault condition can be cleared by writing a ?1? to the faultclr bit in the faultcontrol write register group. (this does not automatically re-enable pwm output.) byte offset bit position 7 6 5 4 3 2 1 0 0x1e spare exectm flt ovrspdflt ovflt lvflt gatekillflt faultstatus read register map field name access (r/w) field description gatekillflt r filtered and latched version of ir213x fault output. lvflt r dc bus low voltage fault. this fault occurs if the dc bus drops below 120v. ovflt r dc bus overvoltage fault. this fault occurs if the dc bus voltage exceeds 410v. ovrspdflt r over speed fault. this fault occu rs whenever the motor reaches the positive or negative limits. the user should use the scale factor in the spdscl field of the velocityc ontrol write register group to scale the motor speed so that it falls between -16384 and +16383 with these limits as the over speed condition. exectmflt r execution time fault. faultstatus read regist er field definitions v v e e l l o o c c i i t t y y s s t t a a t t u u s s r r e e g g i i s s t t e e r r g g r r o o u u p p ( ( r r e e a a d d r r e e g g i i s s t t e e r r s s ) ) byte offset bit position 7 6 5 4 3 2 1 0 0x26 spd (lsbs) 0x27 spd (msbs) velocitystatus read register map
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 55 field name access (r/w) field description spd r current motor speed in speed units. (see the description of spdscl in the velocitycontrol write register group.) velocitystatus read register field definitions c c u u r r r r e e n n t t f f e e e e d d b b a a c c k k o o f f f f s s e e t t r r e e g g i i s s t t e e r r g g r r o o u u p p ( ( r r e e a a d d r r e e g g i i s s t t e e r r s s ) ) byte offset bit position 7 6 5 4 3 2 1 0 0x30 ifbvoffs (lsbs) (r) 0x31 ifbwoffs (lsbs) (r) ifbvoffs (msbs) (r) 0x32 ifbwoffs (msbs) (r) currentfeedbackoffset read register map field name access (r/w) field description ifbvoffs, ifbwoffs r current feedback offset values from t he last ifb offset calculation. these values are automatically applied to each current feedback measurement value whenever the ifboffsenb bit in the systemcontrol write register group is set. currentfeedbackoffset read register field definitions 3 3 2 2 b b i i t t q q u u a a d d d d e e c c o o d d e e s s t t a a t t u u s s r r e e g g i i s s t t e e r r g g r r o o u u p p ( ( r r e e a a d d r r e e g g i i s s t t e e r r s s ) ) byte offset bit position 7 6 5 4 3 2 1 0 0x34 enccnt32br (bits 0-7) (r) 0x35 enccnt32br (bits 8-15) (r) 0x36 enccnt32br (bits 16-23) (r) 0x37 enccnt32br (bits 24-31) (r) 32bitquaddecodestatus read register map
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 56 field name access (r/w) field description enccnt32br r current value of 32- bit quadrature decoder counter. 32bitquaddecodestatus read register field definitions e e e e p p r r o o m m s s t t a a t t u u s s r r e e g g i i s s t t e e r r s s ( ( r r e e a a d d r r e e g g i i s s t t e e r r s s ) ) byte offset bit position 7 6 5 4 3 2 1 0 0x38 spare eebusy 0x39 eedatar (r) 0x3a eeaddrr (r) 0x3b regmapver (r) eepromstatus read register map field name access (r/w) field description eebusy r i2c eeprom interface busy bit. t he user should wait for this bit to clear before initiating eeprom read or write operations. eedatar r eeprom data register. contains the data from the last eeprom read operation. note that writing to the eerst field in the eepromcontrol write register gr oup invalidates this register. eeaddrr r eeprom address read register shows the value stored in eeprom at the offset of the eeaddrw writ e register (0x5d). since this address in the eeprom contains the bpfpga register map version, the user can read this fi eld to determine whether or not the write registers were initialized at power on. regmapver r current register map version code. eepromstatus read register field definitions
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 57 f f o o c c d d i i a a g g n n o o s s t t i i c c d d a a t t a a s s u u p p p p l l e e m m e e n n t t r r e e g g i i s s t t e e r r g g r r o o u u p p ( ( r r e e a a d d r r e e g g i i s s t t e e r r s s ) ) byte offset bit position 7 6 5 4 3 2 1 0 0x3c elecangr (lsbs) (r) 0x3d spare elecangr (msbs) (r) 0x3e spdref (lsbs) (r) 0x3f spdref (msbs) (r) 0x40 spderr (lsbs) (r) 0x41 spderr (msbs) (r) 0x42 iqrefr (lsbs) (r) 0x43 iqrefr (msbs) (r) focdiagnosticdatasupplement read register map field name access (r/w) field description elecangr r electrical angle. spdref r speed pi controller reference input. spderr r speed pi controller error. iqrefr r speed pi controller output. focdiagnosticdatasupplement read register field definitions
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 58 appendix b package 51 35 1 34 qfp100 33 32 31 30 29 28 27 26 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 36 37 38 39 40 41 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 e b h d d e h e 17 18 19 20 21 22 23 24 25 44 43 42 45 46 47 48 49 50 67 68 69 70 71 72 73 74 75 78 77 76 79 81 80 82 83 84 85 86 87 88 89 90 91 100 99 92 93 94 95 96 97 98 o 2 a2 l l2 r r 1 l1 a1 o 3 index a table 24: qfp100 package
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 59 dimension in milimeters dimension in inches* symbol min. nom. max. min. nom. max. e 13.9 14 14.1 (0.548) (0.551) (0.555) d 13.9 14 14.1 (0.548) (0.551) (0.555) a 1.7 (0.066) a1 0.1 (0.004) a2 1.3 1.4 1.5 (0.052) (0.055) (0.059) e 0.5 (0.020) b 0.13 0.18 0.28 (0.006) (0.007) (0.011) c 0.1 0.125 0.175 (0.004) (0.005) (0.006) 0o 10o (0o) (10o) l 0.3 0.5 0.7 (0.012) (0.20) (0.027) l1 1 (0.039) l2 0.5 (0.020) h e 15.6 16 16.4 (0.615) (0.630) (0.645) h d 15.6 16 16.4 (0.615) (0.630) (0.645) o2 12o (12o) o3 12o (12o) r 0.2 (0.008) r1 0.2 (0.008) table 25: qfp100 dimensions * for reference
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 60 appendix c errata 1. using the ads7818 a/d converter interface as the current feedback source is not supported 2. the scaling is too large by a factor of 16 for the following diagnostic dac pwm selections: reference speed (pwm data select value of 5), motor speed (pwm data select value of 6), iqref (pwm data select value of 8). the scaling is too large by a factor of 8 for the following diagnostic dac pwm selections: iq (pwm data select value of 12), id (pwm data select value of 13). the scaling is too large by a factor of 4 for the following diagnostic dac pwm selections: av (pwm data select value of 14), bv (pwm data select value of 15). these values will work at small data ranges, but overflow otherwise. to extract the correct data for these items, use the parallel port and diagnostic data registers. 3. when the IRMCK201 is implemented in conjunction with the ads7818, note that the IRMCK201 adclk is specified at 120 ns while the ads7818 is specified at 125 ns.
IRMCK201 this document is the property of international rectifier and ma y not be copied or distributed without expressed consent. 61 ir world headquarters: 233 kansas st., el segundo, california 90245, tel: (310) 252-7105 http://www.irf.com data and specifications subject to change without notice. 9/15/2003 sales offices, agents and distributors in major cities throughout the world.

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